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CY7C4421/4201/4211/4221 CY7C4231/4241/425164/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4421/4201/4211/4221 CY7C4231/4241/4251
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Features
* High-speed, low-power, First-In, First-Out (FIFO) memories -- 64 x 9 (CY7C4421) -- 256 x 9 (CY7C4201) -- 512 x 9 (CY7C4211) -- 1K x 9 (CY7C4221) -- 2K x 9 (CY7C4231) -- 4K x 9 (CY7C4241) -- 8K x 9 (CY7C4251) * High-speed 100-MHz operation (10 ns Read/Write cycle time) * Low power (ICC = 35 mA) * Fully asynchronous and simultaneous Read and Write operation * Empty, Full, and Programmable Almost Empty and Almost Full status flags * TTL-compatible * Expandable in width * Output Enable (OE) pin * Independent Read and Write enable pins * Center power and ground pins for reduced noise * Width-expansion capability * Space saving 7 mm x 7 mm 32-pin TQFP * Pin-compatible and functionally equivalent to IDT72421, 72201, 72211, 72221, 72231, and 72241 * Pb-Free Packages Available
Functional Description
The CY7C42X1 are high-speed, low-power FIFO memories with clocked Read and Write interfaces. All are 9 bits wide. The CY7C42X1 are pin-compatible to IDT722X1. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and two Write-enable pins (WEN1, WEN2/LD). When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a free-running Read clock (RCLK) and two Read-enable pins (REN1, REN2). In addition, the CY7C42X1 has an output enable pin (OE). The Read (RCLK) and Write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous Read/Write applications. Clock frequencies up to 100 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data.
Logic Block Diagram
D0 - 8
Pin Configurations
PLCC Top View
4 3 2 1 32 3130 29 5 28 6 27 7 26 8 9 25 10 24 11 23 12 22 21 13 141516 171819 20
WCLK WEN1 WEN2/LD FLAG PROGRAM REGISTER Write CONTROL FLAG LOGIC Dual Port RAM Array 64 x 9 Write POINTER 8k x 9 Read POINTER EF PAE PAF FF
D1 D0 PAF PAE GND REN1 RCLK REN2 OE
D2 D3 D4 D5 D6 D7 D8
RS WEN1 WCLK WEN2/LD V CC Q8 Q7 Q6 Q5
INPUT REGISTER
D 3 EF D 4 FF Q D5 0 Q1 D6 Q 2 D7 Q 3 D8 Q4 RS
TQFP Top View
24 23 22 21 20 19 18 17 WEN1 WCLK WEN2/LD VCC Q8 Q7 Q6 Q5
D1 D0 PAF PAE GND REN1 RCLK REN2
RS
RESET LOGIC
THREE-ST ATE OUTPUT REGISTER OE Q0 - 8
Read CONTROL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D2
32 31 30 29 28 27 26 25
FF Q0 Q1
Q2
RCLK REN1 REN2
Cypress Semiconductor Corporation Document #: 38-06016 Rev. *C
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised August 2, 2005
OE EF
Q3 Q4
CY7C4421/4201/4211/4221 CY7C4231/4241/4251
Selection Guide
-10 Maximum Frequency Maximum Access Time Minimum Cycle Time Minimum Data or Enable Set-up Minimum Data or Enable Hold Maximum Flag Delay Active Power Supply Current Commercial Industrial CY7C4421 Density 64 x 9 CY7C4201 256 x 9 CY7C4211 512 x 9 100 8 10 3 0.5 8 35 40 CY7C4221 1K x 9 -15 66.7 10 15 4 1 10 35 40 CY7C4231 2K x 9 -25 40 15 25 6 1 15 35 40 CY7C4241 4K x 9 CY7C4251 8K x 9 Unit MHz ns ns ns ns ns ICC1
Pin Definitions
Pin D0-8 Q0-8 WEN1 Name Data Inputs Data Outputs Write Enable 1 I/O I O I Data Inputs for 9-bit Bus Data Outputs for 9-bit Bus The only Write enable to have programmable flags when device is configured. Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH. If the FIFO is configured to have two Write enables, data is written on a LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH. If HIGH at reset, this pin operates as a second Write enable. If LOW at reset, this pin operates as a control to Write or Read the programmable flag offsets. WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. Enables Device for Read Operation The rising edge clocks data into the FIFO when WEN1 is LOW, WEN2/LD is HIGH, and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-offset register. When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. When FF is LOW, the FIFO is full. FF is synchronized to WCLK. When PAE is LOW, the FIFO is almost empty based on the almost empty offset value programmed into the FIFO. When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. Resets device to empty condition. A reset is required before an initial Read or Write operation after power-up. When OE is LOW, the FIFO's data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO's outputs are in High-Z (high-impedance) state. Description
WEN2/LD Dual Write Enable 2 Mode Pin Load
I I
REN1, REN2 WCLK
Read Enable Inputs Write Clock
I I
RCLK
Read Clock
I
EF FF PAE PAF RS OE
Empty Flag Full Flag Programmable Almost Empty Programmable Almost Full Reset Output Enable
O O O O I I
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CY7C4421/4201/4211/4221 CY7C4231/4241/4251
Functional Description
The CY7C42X1 provides four status pins: Empty, Full, Almost Empty, Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty - 7 and Full - 7. The flags are synchronous, i.e., they change state relative to either the Read clock (RCLK) or the Write clock (WCLK). When entering or exiting the Empty and Almost Empty states, the flags are updated exclusively by the RCLK. The flags denoting Almost Full, and Full states are updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags maintain their status for at least one cycle. All configurations are fabricated using advanced 0.65 N-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. maintains the data of the last valid Read on its Q0-8 outputs even after additional reads occur. Write Enable 1 (WEN1). If the FIFO is configured for programmable flags, Write Enable 1 (WEN1) is the only Write enable control pin. In this configuration, when Write Enable 1 (WEN1) is LOW, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every Write clock (WCLK). Data is stored is the RAM array sequentially and independently of any on-going Read operation. Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin. The FIFO is configured at Reset to have programmable flags or to have two Write enables, which allows for depth expansion. If Write Enable 2/Load (WEN2/LD) is set active HIGH at Reset (RS = LOW), this pin operates as a second Write enable pin. If the FIFO is configured to have two Write enables, when Write Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is HIGH, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every Write clock (WCLK). Data is stored in the RAM array sequentially and independently of any on-going Read operation.
Architecture
The CY7C42X1 consists of an array of 64 to 8K words of 9 bits each (implemented by a dual-port array of SRAM cells), a Read pointer, a Write pointer, control signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF).
Programming
When WEN2/LD is held LOW during Reset, this pin is the load (LD) enable for flag offset programming. In this configuration, WEN2/LD can be used to access the four 8-bit offset registers contained in the CY7C42X1 for writing or reading data to these registers. When the device is configured for programmable flags and both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH transition of WCLK writes data from the data inputs to the empty offset least significant bit (LSB) register. The second, third, and fourth LOW-to-HIGH transitions of WCLK store data in the empty offset most significant bit (MSB) register, full offset LSB register, and full offset MSB register, respectively, when WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH transition of WCLK while WEN2/LD and WEN1 are LOW writes data to the empty LSB register again. Figure 1 shows the registers sizes and default values for the various device types. It is not necessary to write to all the offset registers at one time. A subset of the offset registers can be written; then by bringing the WEN2/LD input HIGH, the FIFO is returned to normal Read and Write operation. The next time WEN2/LD is brought LOW, a Write operation stores data in the next offset register in sequence. The contents of the offset registers can be read to the data outputs when WEN2/LD is LOW and both REN1 and REN2 are LOW. LOW-to-HIGH transitions of RCLK Read register contents to the data outputs. Writes and reads should not be preformed simultaneously on the offset registers.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs (Q0-8) go LOW tRSF after the rising edge of RS. In order for the FIFO to reset to its default state, a falling edge must occur on RS and the user must not read or Write while RS is LOW. All flags are guaranteed to be valid tRSF after RS is taken LOW.
FIFO Operation
When the WEN1 signal is active LOW and WEN2 is active HIGH, data present on the D0-8 pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the REN1 and REN2 signals are active LOW, data in the FIFO memory will be presented on the Q0-8 outputs. New data will be presented on each rising edge of RCLK while REN1 and REN2 are active. REN1 and REN2 must set up tENS before RCLK for it to be a valid Read function. WEN1 and WEN2 must occur tENS before WCLK for it to be a valid Write function. An output enable (OE) pin is provided to three-state the Q0-8 outputs when OE is asserted. When OE is enabled (LOW), data in the output register will be available to the Q0-8 outputs after tOE. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO
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64 x 9 8 65 0 8 256 x 9 7
Empty Offset (LSB) Reg. Default Value = 007h
512 x 9 0 8 7
Empty Offset (LSB) Reg. Default Value = 007h
1K x 9 0 8 7
Empty Offset (LSB) Reg. Default Value = 007h
0
Empty Offset (LSB) Reg. Default Value = 007h
8
0
8
0
8
1
(MSB) 0
0
8
1
(MSB) 00
0
8
65
Full Offset (LSB) Reg Default Value = 007h
0
8
7
Full Offset (LSB) Reg Default Value = 007h
0
8
7
Full Offset (LSB) Reg Default Value = 007h
0
8
7
Full Offset (LSB) Reg Default Value = 007h
0
8
0
8
0
8
1
(MSB) 0
0
8
1
(MSB) 00
0
2K x 9 8 7
Empty Offset (LSB) Reg. Default Value = 007h
4K x 9 0 8 7
Empty Offset (LSB) Reg. Default Value = 007h
8K x 9 0 8 7
Empty Offset (LSB) Reg. Default Value = 007h
0
8
2
(MSB) 000
0
8
3
(MSB) 0000
0
8
4
(MSB) 00000
0
8
7
Full Offset (LSB) Reg Default Value = 007h
0
8
7
Full Offset (LSB) Reg Default Value = 007h
0
8
7
Full Offset (LSB) Reg Default Value = 007h
0
8
2
(MSB) 000
0
8
3
(MSB) 0000
0
8
4
(MSB) 00000
0
Figure 1. Offset Register Location and Default Values
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Programmable Flag (PAE, PAF) Operation Whether the flag offset registers are programmed as described in Table 1 or the default values are used, the programmable almost-empty flag (PAE) and programmable almost-full flag (PAF) states are determined by their corresponding offset registers and the difference between the Read and Write pointers. The number formed by the empty offset least significant bit register and empty offset most significant register is referred to as n and determines the operation of PAE. PAE is synchronized to the LOW-to-HIGH transition of RCLK by one flip-flop and is LOW when the FIFO contains n or fewer unread words. PAE is set HIGH by the LOW-to-HIGH transition of RCLK when the FIFO contains (n + 1) or greater unread words. The number formed by the full offset least significant bit register and full offset most significant bit register is referred to as m and determines the operation of PAF. PAE is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4421. (64 - m), CY7C4201 Table 2. Status Flags Number of Words in FIFO CY7C4421 0 1 to n[2] (n + 1) to 32 33 to (64 - (m + 1)) (64 - m)[3] to 63 64 0 1 to n[2] (n + 1) to 128 129 to (256 - (m + 1)) (256 - m)[3] to 255 256 CY7C4201 0 1 to n[2] (n + 1) to 256 257 to (512 - (m + 1)) (512 - m)[3] to 511 512 Number of Words in FIFO CY7C4221 0 1 to n[2] (n + 1) to 512 (1024 - 1024 m)[3] to 1023 0 1 to n[2] (n + 1) to 1024 (2048 - 2048 m)[3] to 2047 CY7C4231 0 1 to n[2] (n + 1) to 2048 (4096 - 4096 m)[3] to 4095 CY7C4241 0 1 to n[2] (n + 1) to 4096 (8192 - 8192 m)[3] to 8191 CY7C4251 FF H H H H H L PAF H H H H L L PAE L L H H H H EF L H H H H H CY7C4211 FF H H H H H L PAF H H H H L L PAE L L H H H H EF L H H H H H (256 - m), CY7C4211 (512 - m), CY7C4221 (1K - m), CY7C4231 (2K - m), CY7C4241 (4K - m), and CY7C4251 (8K - m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m. Table 1. Writing the Offset Registers LD 0 WEN 0 WCLK[1] Selection Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) No Operation Write Into FIFO No Operation
0 1 1
1 0 1
513 to (1024 - (m + 1)) 1025 to (2048 - (m + 1)) 2049 to (4096 - (m + 1)) 4097 to (8192 - (m + 1))
Notes: 1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a Read is performed on the LOW-to-HIGH transition of RCLK. 2. n = Empty Offset (n = 7 default value). 3. m = Full Offset (m = 7 default value).
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Width Expansion Configuration
Word width may be increased simply by connecting the corresponding input controls signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF). The partial status flags (PAE and PAF) can be detected from any one device. Figure 2 demonstrates a 18-bit word width by using two CY7C42X1s. Any word width can be attained by adding additional CY7C42X1s. When the CY7C42X1 is in a Width Expansion Configuration, the Read Enable (REN2) control input can be grounded (See Figure 2). In this configuration, the Write Enable 2/Load (WEN2/LD) pin is set to LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets.
Flag Operation
The CY7C42X1 devices provide four flag pins to indicate the condition of the FIFO contents. Empty, Full, PAE, and PAF are synchronous. Full Flag The Full Flag (FF) will go LOW when device is full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e., it is exclusively updated by each rising edge of WCLK. Empty Flag The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN1 and REN2. EF is synchronized to RCLK, i.e., it is exclusively updated by each rising edge of RCLK.
RESET (RS) DATA IN (D) 18 Write Write Write
9 9
RESET (RS) Read CLOCK (RCLK) Read ENABLE 1 (REN1) OUTPUT ENABLE (OE) PROGRAMMABLE (PAE) EMPTY FLAG (EF) #1 EF EMPTY FLAG (EF) #2 FF
9 9
CLOCK (WCLK)
ENABLE 1 (WEN1) ENABLE 2/LOAD (WEN2/LD)
CY7C42X1 CY7C42X1
PROGRAMMABLE (PAF) FULL FLAG (FF) # 1 FULL FLAG (FF) # 2 FF
EF
DATA OUT (Q)
18
Read Enable 2 (REN2)
Read Enable 2 (REN2)
Figure 2. Block Diagram of 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 Synchronous FIFO Memory Used in a Width Expansion Configuration
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Maximum Ratings[4]
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ...................................-65C to +150C Ambient Temperature with Power Applied...............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State ............................................... -0.5V to +7.0V DC Input Voltage............................................ -3.0V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA
Operating Range
Range Commercial Industrial
[5]
Ambient Temperature 0C to +70C -40C to +85C
VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range[6]
-10 Parameter VOH VOL VIH VIL IIX IOS[7] IOZL IOZH ICC1[8] ICC2[9] Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Short Circuit Current Output OFF, High-Z Current Active Power Supply Current Average Standby Current VCC = Max. VCC = Max., VOUT = GND OE > VIH, VSS < VO < VCC Commercial Industrial Commercial Industrial Test Conditions VCC = Min., IOH = -2.0 mA VCC = Min., IOL = 8.0 mA 2.2 -3.0 -10 -90 -10 +10 35 40 10 15 Min. 2.4 0.4 VCC 0.8 +10 2.2 -3.0 -10 -90 -10 +10 35 40 10 15 Max. Min. 2.4 0.4 VCC 0.8 +10 2.2 -3.0 -10 -90 -10 +10 35 40 10 15 -15 Max. Min. 2.4 0.4 VCC 0.8 +10 -25 Max. Unit V V V V A mA mA mA mA mA mA
Capacitance[10]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 5 7 Unit pF pF
Notes: 4. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 5. TA is the "instant on" case temperature. 6. See the last page of this specification for Group A subgroup testing information. 7. Test no more than one output at a time for not more than one second. 8. Outputs open. Tested at Frequency = 20 MHz. 9. All inputs = VCC - 0.2V, except WCLK and RCLK, which are switching at 20 MHz. 10. Tested initially and after any design or process changes that may affect these parameters.
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AC Test Loads and Waveforms[11, 12]
R1 1.1 K 5V OUTPUT CL INCLUDING JIG AND SCOPE R2 680 Equivalent to: 3.0V GND 3 ns THEVENIN EQUIVALENT 420 OUTPUT
ALL INPUT PULSES
90% 10% 90% 10% 3 ns
1.91V
Switching Characteristics Over the Operating Range
-10 Parameter tS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tRSF tOLZ tOE tOHZ tWFF tREF tPAF tPAE tSKEW1 tSKEW2 Description Clock Cycle Frequency Data Access Time Clock Cycle Time Clock HIGH Time Clock LOW Time Data Set-up Time Data Hold Time Enable Set-up Time Enable Hold Time Reset Pulse Width[13] Reset Set-up Time Reset Recovery Time Reset to Flag and Output Time Output Enable to Output in Low-Z[14] Output Enable to Output Valid Output Enable to Output in High-Z[14] Write Clock to Full Flag Read Clock to Empty Flag Clock to Programmable Almost-Full Flag Clock to Programmable Almost-Full Flag Skew Time between Read Clock and Write Clock for Empty Flag and Full Flag Skew Time between Read Clock and Write Clock for Almost-Empty Flag and Almost-Full Flag 5 10 0 3 3 7 7 8 8 8 8 6 15 2 10 4.5 4.5 3 0.5 3 0.5 10 8 8 10 0 3 3 8 8 10 10 10 10 10 18 Min. Max. 100 8 2 15 6 6 4 1 4 1 15 10 10 15 0 3 3 12 12 15 15 15 15 Min. -15 Max. 66.7 10 2 25 10 10 6 1 6 1 25 15 15 25 Min. -25 Max. 40 15 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 11. CL = 30 pF for all AC parameters except for tOHZ. 12. CL = 5 pF for tOHZ. 13. Pulse widths less than minimum values are not allowed. 14. Values guaranteed by design, not currently tested.
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Switching Waveforms
Write Cycle Timing
tCLK
tCLKH WCLK
tCLKL
tDS D0 -D8 tENS WEN1
tDH
tENH
NO OPERATION
WEN2 (if applicable) FF tSKEW1 RCLK
[15]
NO OPERATION
tWFF
tWFF
REN1,REN2
Read Cycle Timing
tCKL
tCLKH RCLK tENS REN1,REN2 tREF EF tA Q0 -Q8 tOLZ OE tOE tENH
tCLKL
NO OPERATION
tREF
VALID DATA
tOHZ
tSKEW1 WCLK WEN1
[16]
WEN2
Notes: 15. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge. 16. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK rising edge.
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Switching Waveforms (continued)
Reset Timing[17]
tRS tRSS REN1, REN2 tRSS WEN1 tRSS WEN2/LD
[18]
RS
tRSR
tRSR
tRSR
tRSF EF,PAE tRSF FF,PAF, tRSF Q0 - Q8 OE = 1 [19] OE = 0
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
t DS
D 0 -D8
tENS
D0 (FIRSTVALID Write)
[20]
D1
D2
D3
D4
WEN1 WEN2 (if applicable)
tSKEW1
tFRL
RCLK
tREF
EF REN1, REN2 Q0 -Q8
tOLZ tOE
tA
[21]
tA
D0
D1
OE
Notes: 17. The clocks (RCLK, WCLK) can be free-running during reset. 18. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers. 19. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1. 20. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW). 21. The first word is available the cycle after EF goes HIGH, always.
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Switching Waveforms (continued)
Empty Flag Timing
WCLK tDS D0 -D8 tENS WEN1 DATAWRITE1 tENH tENS tDS DATAWRITE2 tENH
WEN2 (if applicable)
tENS
tENH
tFRL
[20]
tENS
tENH
tFRL
[20]
RCLK tSKEW1 EF REN1, REN2 LOW OE tA Q0 -Q8 DATA IN OUTPUT REGISTER DATA Read tREF tREF tSKEW1 tREF
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Switching Waveforms (continued)
Full Flag Timing
NO Write WCLK tSKEW1[15] D0 -D8 tWFF FF tDS DATA Write tWFF tWFF tSKEW1[15] DATA Write NO Write NO Write
WEN1 WEN2 (if applicable)
RCLK tENS tENH tENS tENH
REN1, REN2
OE
LOW tA tA DATA Read NEXT DATA Read
Q0 -Q8
DATA IN OUTPUT REGISTER
Programmable Almost Empty Flag Timing
tCLKH WCLK tENS tENH WEN1 WEN2 (if applicable) tENS tENH PAE tSKEW2[22] RCLK tENS REN1, REN2
Notes: 22. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK. 23. PAE offset = n. 24. If a Read is performed on this rising edge of the Read clock, there will be Empty + (n - 1) words in the FIFO when PAE goes LOW.
tCLKL
Note 23 tPAE
N + 1 WORDS INFIFO
Note 24
tPAE
tENS tENH
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Switching Waveforms (continued)
Programmable Almost Full Flag Timing
Note 25
tCLKH WCLK
tCLKL
tENS tENH WEN1 WEN2 (if applicable) tENS tENH PAF FULL - M+1 WORDS IN FIFO Note 26 tPAF FULL - M WORDS IN FIFO[27] tSKEW2 [28] tPAF
RCLK tENS REN1, REN2 tENS tENH
Write Programmable Registers
tCLK tCLKH WCLK tENS WEN2/LD tENS WEN1 tDS D0 -D8 PAE OFFSET LSB PAE OFFSET MSB PAF OFFSET LSB PAF OFFSET MSB tDH tENH tCLKL
Notes: 25. If a Write is performed on this rising edge of the Write clock, there will be Full - (m - 1) words of the FIFO when PAF goes LOW. 26. PAF offset = m. 27. 64-m words for CY7C4421, 256 - m words in FIFO for CY7C4201, 512 - m words for CY7C4211, 1024 - m words for CY7C4221, 2048 - m words for CY7C4231, 4096 - m words for CY7C4241, 8192 - m words for CY7C4251. 28. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.
Document #: 38-06016 Rev. *C
Page 13 of 19
CY7C4421/4201/4211/4221 CY7C4231/4241/4251
Switching Waveforms (continued)
Read Programmable Registers
tCLK tCLKH RCLK tENS WEN2/LD tENS REN1, REN2 tA Q0 -Q8 UNKNOWN PAE OFFSET LSB PAE OFFSET MSB PAF OFFSET LSB PAF OFFSET MSB tENH tCLKL
Document #: 38-06016 Rev. *C
Page 14 of 19
CY7C4421/4201/4211/4221 CY7C4231/4241/4251
Typical AC and DC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC NORMALIZED ICC 1.2 1.0 0.8 0.6 4 VIN = 3.0V TA = 25C f = 100 MHz 4.5 5 5.5 6 1.20 NORMALIZED ICC 1.10 1.00 0.90 0.80 -55 VIN = 3.0V VCC = 5.0V f = 100 MHz NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.10 1.00 0.90 0.80 0.70 0.60 0 25 50 75 100 NORMALIZED SUPPLY CURRENT vs. FREQUENCY VCC = 5.0V TA = 25C VIN = 3.0V
25
125
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C) NORMALIZED tA vs. AMBIENT TEMPERATURE 1.50 NORMALIZED tA 1.25 1.00 0.75 0.50 -55 VCC = 5.0V Delta tA (ns) 25 40
FREQUENCY (MHz) TYPICAL tA CHANGE vs. OUTPUT LOADING
NORMALIZED tA vs. SUPPLY VOLTAGE 1.2 NORMALIZED tA 1.1 1.0 0.9 0.8 4 4.5 5 5.5 6 SUPPLY VOLTAGE (V) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 55 45 35 25 0 1 2 3 4 OUTPUT VOLTAGE (V)
10
0 25 125 0 200
VCC = 5.0V TA = 25C 400 600 800 1000 CAPACITANCE (pF)
AMBIENT TEMPERATURE (C) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 160 140 120 100 80 60 40 20 0
OUTPUT SOURCE CURRENT (mA)
OUTPUT SINK CURRENT (mA)
0
1
2
3
4
OUTPUT VOLTAGE (V)
Document #: 38-06016 Rev. *C
Page 15 of 19
CY7C4421/4201/4211/4221 CY7C4231/4241/4251
Ordering Information
64 x 9 Synchronous FIFO Speed (ns) 10 Ordering Code CY7C4421-10AC CY7C4421-10JC CY7C4421-10JXC 15 CY7C4421-15AC CY7C4421-15JC 256 x 9 Synchronous FIFO Speed (ns) 10 15 Ordering Code CY7C4201-10AC CY7C4201-10JC CY7C4201-15AC CY7C4201-15AXC CY7C4201-15JC CY7C4201-15JXC 25 CY7C4201-25AC CY7C4201-25JC CY7C4201-25AI 512 x 9 Synchronous FIFO Speed (ns) 10 Ordering Code CY7C4211-10AC CY7C4211-10JC CY7C4211-10AI CY7C4211-10AXI CY7C4211-10JI 15 CY7C4211-15AC CY7C4211-15AXC CY7C4211-15JC CY7C4211-15JXC CY7C4211-15AI 25 CY7C4211-25AC CY7C4211-25JC 1K x 9 Synchronous FIFO Speed (ns) 10 15 Ordering Code CY7C4221-10AC CY7C4221-10JC CY7C4221-15AC CY7C4221-15AXC CY7C4221-15JC CY7C4221-15JXC 25 CY7C4221-25AC CY7C4221-25JC Document #: 38-06016 Rev. *C Package Name A32 J65 A32 A32 J65 J65 A32 J65 Package Type 32-lead Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Thin Quad Flatpack 32-lead Pb-Free Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Pb-Free Plastic Leaded Chip Carrier 32-lead Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier Page 16 of 19 Commercial Commercial Operating Range Commercial Package Name A32 J65 A32 A32 J65 A32 A32 J65 J65 A32 A32 J65 Package Type 32-lead Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Thin Quad Flatpack 32-lead Pb-Free Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Thin Quad Flatpack 32-lead Pb-Free Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Pb-Free Plastic Leaded Chip Carrier 32-lead Thin Quad Flatpack 32-lead Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier Industrial Commercial Commercial Industrial Operating Range Commercial Package Name A32 J65 A32 A32 J65 J65 A32 J65 A32 Package Type 32-lead Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Thin Quad Flatpack 32-lead Pb-Free Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Pb-Free Plastic Leaded Chip Carrier 32-lead Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Thin Quad Flatpack Industrial Commercial Commercial Operating Range Commercial Package Name A32 J65 J65 A32 J65 Package Type 32-lead Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Pb-Free Plastic Leaded Chip Carrier 32-lead Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier Commercial Operating Range Commercial
CY7C4421/4201/4211/4221 CY7C4231/4241/4251
2K x 9 Synchronous FIFO Speed (ns) 10 15 Ordering Code CY7C4231-10AC CY7C4231-10JC CY7C4231-15AC CY7C4231-15AXC CY7C4231-15JC CY7C4231-15JXC 25 CY7C4231-25AC CY7C4231-25JC 4K x 9 Synchronous FIFO Speed (ns) 10 Ordering Code CY7C4241-10AC CY7C4241-10AXC CY7C4241-10JC CY7C4241-10JI 15 CY7C4241-15AC CY7C4241-15AXC CY7C4241-15JC CY7C4241-15JXC 25 CY7C4241-25AC CY7C4241-25JC CY7C4241-25JI 8K x 9 Synchronous FIFO Speed (ns) 10 Ordering Code CY7C4251-10AC CY7C4251-10JC CY7C4251-10JXC CY7C4251-10AI CY7C4251-10AXI 15 CY7C4251-15AC CY7C4251-15AXC CY7C4251-15JC CY7C4251-15JXC 25 CY7C4251-25AC CY7C4251-25JC CY7C4251-25AI Package Name A32 J65 J65 A32 A32 A32 A32 J65 J65 A32 J65 A32 Package Type 32-lead Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Pb-Free Plastic Leaded Chip Carrier 32-lead Thin Quad Flatpack 32-lead Pb-Free Thin Quad Flatpack 32-lead Thin Quad Flatpack 32-lead Pb-Free Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Pb-Free Plastic Leaded Chip Carrier 32-lead Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Thin Quad Flatpack Industrial Commercial Commercial Industrial Operating Range Commercial Package Name A32 A32 J65 J65 A32 A32 J65 J65 A32 J65 J65 Package Type 32-lead Thin Quad Flatpack 32-lead Pb-Free Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Plastic Leaded Chip Carrier 32-lead Thin Quad Flatpack 32-lead Pb-Free Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Pb-Free Plastic Leaded Chip Carrier 32-lead Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Plastic Leaded Chip Carrier Industrial Commercial Industrial Commercial Operating Range Commercial Package Name A32 J65 A32 A32 J65 J65 A32 J65 Package Type 32-lead Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Thin Quad Flatpack 32-lead Pb-Free Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier 32-lead Pb-Free Plastic Leaded Chip Carrier 32-lead Thin Quad Flatpack 32-lead Plastic Leaded Chip Carrier Commercial Commercial Operating Range Commercial
Document #: 38-06016 Rev. *C
Page 17 of 19
CY7C4421/4201/4211/4221 CY7C4231/4241/4251
Package Diagrams
32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32 32-lead Pb-Free Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32
51-85063-*B
32-Lead Pb-Free Plastic Leaded Chip Carrier J65 32-Lead Plastic Leaded Chip Carrier J65
51-85002-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-06016 Rev. *C
Page 18 of 19
(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C4421/4201/4211/4221 CY7C4231/4241/4251
Document Title: CY7C4421/4201/4211/4221, CY7C4231/4241/4251 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs Document Number: 38-06016 REV. ** *A *B *C ECN NO. 106477 110725 122268 386306 Issue Date 09/10/01 03/20/02 12/26/02 See ECN Orig. of Change SZV FSG RBI ESH Description of Change Change from Spec number: 38-00419 to 38-06016 Change Input Leakage current IIX unit from mA to A (typo) Power up requirements added to Maximum Ratings Information Added Pb-Free logo to top of front page Added CY7C4421-10JXC, CY7C4201-15AXC. CY7C4201-15JXC, CY7C4211-10AXI, CY7C4211-15AXC, CY7C4211-15JXC, CY7C4221-15AXC, CY7C4221-15JXC, CY7C4231-15JXC, CY7C4231-15AXC, CY7C4241-10AXC, CY7C4241-15AXC, CY7C4241-15JXC, CY7C4251-10JXC, CY7C4251-10AXI, CY7C4251-15AXC, CY7C4251-15JXC
Document #: 38-06016 Rev. *C
Page 19 of 19

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